DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.2.25. Variable-Size Supersampled FFT

This DSP Builder design example implements a variable-size supersampled FFT, with sizes ranging from 256 to 2,048 points, and a parallelism of 4 wires.

The incoming data is of fixed-point type and arrives in natural order. The number of radix-2 stages assigned to the serial section of the hybrid FFT is 7.