DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.8.1. Avalon-ST Interface (Input and Output FIFO Buffer) with Backpressure

This example demonstrates the Avalon-ST input interface with FIFO buffers and the AvalonST output interface blocks. This example has FIFO buffers in the input and output interfaces. Use the manual switches in the testbench to change when downstream is ready for data or to turn off input. The simulation ends by turning off incoming data and ensures that it writes out as many valid data cycles as it receives.

The model file is demo_avalon_st_input_fifo.mdl.

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