DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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4.3.2. Managing Bit Growth in DSP Builder Advanced Blockset Designs

Manage bit growth after you update your design or run a simulation.


  1. To display the signal type and width turn on Simulink display of signal types.
  2. Manage and control bit width at various stages of your design, either because of hardware resource limitation or fMAX speed concerns.
  3. Track bit growth by studying the algorithm and determining bit width at various stage of the design from the mathematical model of the design.
  4. Use Simulink Fixed-Point Toolbox to visualize the bit width distribution at various places of the design. The fixed-point toolbox displays the histogram of datapath signals you log.
  5. To log a data signal in your Simulink design, right-click on the wire and select Signal Properties.
  6. With the histogram decide how many MSBs are unused in the current fixed-point representation, which helps you decide how many MSBs to discard, thus maximizing the dynamic range of your scaled data.

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