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- 15.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 15.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
7.12.1. 16-Channel DDC
Decimating CIC and FIR filters down convert eight complex carriers (16 real channels) from 61.44 MHz. The total decimation rate is 64. A real mixer and NCO isolate the eight carriers. The testbench isolates two channels of data from the TDM signals using a channel viewer.
The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_ddc.m script.
The DDCChip subsystem includes Device, Decimating FIR, DecimatingCIC, Mixer, NCO, Scale, RegBit, and RegField blocks.
The model file is demo_ddc.mdl.
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