DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

15.5.2. Channel Out (ChannelOut)

The ChannelOut block delineates the output boundary of a DSP Builder synthesizable Primitive subsystem.

The ChannelOut block passes its input through to the outputs unchanged, with types preserved. This block indicates to DSP Builder that these signals must synchronize, which the synthesis tool can ensure.

When you run a simulation in Simulink, DSP Builder adds additional latency from the balanced pipelining stages to meet the specified timing constraints for your model. The block accounts for this additional latency. This latency does not include any delay explicitly added to your model, by for example a SampleDelay block, just added pipelining for timing closure.

Note: You can also access the value of the latency parameter by typing a command of the following form on the MATLAB command line:


Table 263.  Parameters for the ChannelOut Block
Parameter Description
Number of data signals Specifies the number of data signals on this block.


Table 264.  Port Interface for the ChannelOut Block
Signal Direction Type Description Vector Data Support Complex Data Support
v Input Boolean Valid output signal No No
c Input 8-bit unsigned integer Channel output signal No No
d0, d1, d2, ... Input Any fixed-or floating-point type A number of output data signals Yes Yes
v Output Boolean Valid signal No No
c Output 8-bit unsigned integer Channel signal No No
q0, q1, q2, ... Output Any fixed-or floating-point type A number of data signals Yes Yes