DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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Document Table of Contents

18. Document Revision History for DSP Builder for Intel FPGAs (Advanced Blockset) Handbook

Version Software Version Changes
2022.12.12 22.4
  • Updated DSP Builder Designs in Platform Designer
  • Added Fixed-point Matrix Multiply Engine design
2022.06.20 22.2
  • Updated:
    • Device Support
    • Verifying your DSP Builder Design with C++ Software Models
    • Synthesis Information (SynthesisInfo)
  • Changed Run ModelSim to Run RTL Simulation
  • Removed:
    • New SIL Wizard option
    • Hardware Verification with System-in-the-Loop
2022.05.27 22.1 Added FAQs
2022.04.06 22.1 Removed incorrect info from FIFO
2022.04.04 22.1
  • Added more info to Control Block General Parameters table
  • Added more info to Constant Multiply (Const Mult)
  • Added new parameter and new signal to Shared Memory (SharedMem)
  • Updated Hybrid FFTs
  • Added AXI4-Stream Blocks
2022.03.23 21.3 Added two numerical examples to CORDIC
2021.12.07 21.3 Updated CORDIC
2021.09.30 21.3
  • Added support for Cyclone V devices
  • Removed Bus Slave block references
  • Renamed Avalon-MM slave settings block: to Avalon memory-mapped Agent Settings.
  • Updated DualMem block
  • Added DFT library blocks
2021.03.29 21.1
  • Added Finite State Machine block and design example.
  • Added Simulink Supported Blocks.
2020.10.05 20.3
  • Removed Intel Quartus Prime Standard Edition from Device Support
  • Removed Arria V, Arria V, Arria V GZ, Cyclone IV, Cyclone V, Intel® MAX® 10, Stratix IV, Stratix V from Device Support.
  • Added Intel® Agilex™ devices to Device Support
  • Changed Intel® Cyclone® 10 device support to Intel® Cyclone® 10 GX in Device Support
  • Added new parameter to DualMem block.
  • Added Uninitialized means parameter to Control block.
  • Removed device selector option from Device block.
  • Updated SynthesisInfo block description.
  • Removed GPDependentDelay block.
2020.04.22 20.1 Corrected input type for Lut and Mux blocks
2020.04.15 20.1
  • Updated Using Bit-Accurate Simulation.
  • Updated DSP Builder Testbench Verification.
  • Removed Cholsesky Solver Single Channel.
  • Added Report FIFO fill level parameter to Control.
  • Added more parameters to Control Block Testbenches Tab Parameters
2020.01.06 19.3 Removed "You can also use this option to implement efficient phase-shift keying (PSK) modulators in which the input to the phase modulator varies according to a data stream." from NCO Block
2019.10.31 19.3 Corrected Fanout and VectorFanout descriptions
2019.10.10 19.3
  • Removed all references to standard blockset.
  • Removed DSP Builder Standard and Advanced Blockset Interoperability
  • Added QRD solver reference design
2019.06.10 19.1 Added new parameters to External Memory block.
2019.03.01 19.1
  • Updated supported floating-point data types.
  • Removed "except for Forloop blocks" from Verifying your DSP Builder Design with C++ Software Models
  • Added new parameters to:
    • Sqrt block
    • Control block
  • Removed Using Latency Constraints in DSP Builder Designs
2018.09.17 18.1
  • Updated SharedMem block desccription.
  • Updated:
    • HDL Import feature description.
  • Removed:
    • Running the Simple Complex Multiplication Design Example
    • About the Complex Multilication Design Example
    • Cosimuation Block Parameters
    • Configuring the HDL Import Block Parameters
    • Setting up a Modelsim Cosimulation
    • Adding Ports
    • Adding a HDL Import Block
    • Running a Cosimulation
    • Verifying with HDL Import in the ModelSim
    • Adding HDL Import Design to Intel Quartus Prime
2018.06.27 18.0 Updated Arria 10 to any device with a floating-point block in floating-point designs
2018.06.08 18.0 Added HDL import.
2018.05.09 18.0
  • Added new parameter to Constant block.
  • Added extra description to Fanout block Uninitialized parameter.
  • Added extra info to DualMem block parameters.
  • Added reset minimization feature
  • Added new parameter to SharedMem block.
2017.11.06 17.1
  • Improved description on NCO block Accumulator Bit Width parameter.
  • Corrected parameters on Scalar Product block.
  • Added Forcing Soft Floating-point Data Types with the Advanced Options topic
  • Added super-sample NCO design example.
  • Added support for Intel® Cyclone® 10 and Intel® Stratix® 10 devices.
  • Removed instances of Signals block.
  • Changed input type on GPIn block; changed output type on GPOut block.
  • Deleted WYSIWYG option on SynthesisInfo block.
2017.05.02 17.0
  • Rebranded as Intel
  • Deprecated Signals block
  • Corrected Interpolating FIR Filter design clock to say 240 MHz
  • Added description on how to get output b on decimating, fractional rate, interpolating, and single-rate FIR filters
  • Added Gaussian and Random Number Generator design examples
  • Added variable-size supersampled FFT design example
  • Added HybridVFFT block
  • Added GeneralVTwiddle and GeneralMultVTwiddle blocks
  • Corrected device support and removed Stratix 10 devices.
2016.11.01 16.1
  • Added device support
  • Added 4-channel 2-antenna DUC and DDC for LTE reference design
  • Added BFU_simple block
2016.05.01 16.0
  • Revised getting started
  • Revised design rules
  • Revised setting up Simulink
  • Revised Primitive library description
  • Revised DSP Builder design structure
  • Added a library list
  • Removed Run Quartus and Run ModelSim blocks
  • Moved primitive subsystem designs to avoid from Troubleshooting chapter to Design Rules and Recommendations
  • Moved Troubleshooting to Design Rules, Recommendations, and Troubleshooting.
  • Revised EditParams block description
  • Moved hardware verification from Techniques for Advanced Users to Design Flow chapter
  • Changed threshold names and descriptions on Localthreshold and Control blocks
2016.05.01 cont 16.0 cont
  • Reorganised libraries:
    • Deleted ModelVectorPrim library. Moved SumofElements block to Primitives > Primitives Basic Blocks
    • Renamed Channel library to Channel Filter and Waveform library
    • Renamed Filter chatper to IP chapter
    • Created FFT IP library and added BitReversecoreC, FFT, FFT _Float, VariablebitReverse, VFFT, and VFFT_Float blocks to it.
    • Deleted Waveform Synthesis library and moved blocks into Channel Filter and Waveform library.
    • Renamed Base library to Design Configuration
    • Moved ChanView block from Base to Added transmit and receive modem referenceChannel Filter and Waveform library
    • Moved Scale block from Base to Channel Filter and Waveform library
    • Renamed FFT to FFT Design Elements library and moved to Primitives library
    • Created Primitives Basic Blocks library and move all blocks from Primitive library to it.
    • Created Primitive Configuration library and moved ChannelIn, ChannelOut, GPIn, GPOut, and SynthesisInfo blocks into it.
    • Renamed ModelIP to IP library
    • Renamed ModelBus to Memory Mapped library
    • Renamed ModelBus chapter to Interfaces
    • Created Streaming library and moved the AStInput, AStOutput, and AStInputFIFO blocks into it
    • Renamed Additional to Primitive Design Elements library
    • Renamed Additional chapter to Utilities
    • Created Analyze and Test library and moved Capture Values and Pause blocks to it.
    • Deleted External Memories libray and moved External Memory block to Interfaces > Memory Mapped.
    • Moved DDC Design Example to Design Examples and Reference Design chapter.
2015.11.01 15.1
  • Changed Quartus II to Quartus Prime software
  • Changed Run Quartus II block to Run Quartus Prime block
  • Removed Turn on coverage in testbenches and Signal view depth options from Control block
  • Improved FIR Filter Avalon-MM port descriptions
  • Changed some Avalon-MM Slave Settings block descriptions
  • Added design rules for Modelbus blocks.
  • Added reconfigurable FIR filter information.
  • Removed Enhanced Presicion Support block
  • Removed ScalarProduct graphs
  • Added new blocks:
    • Capture Values
    • Fanout
    • Pause
    • Vectorfanout
  • Added IIR: full-rate fixed-point and IIR: full-rate floating-point demos
  • Changed set_param to dspba.set_param
2015.05.01 15.0
  • Added external memories library
  • Added External Memory block
  • Added new Allow write on both ports parameter to DualMem block
  • Removed read/write note from SharedMem block
  • Changed parameters on AvalonMMSlaveSettings block
  • Added note to latency contraints topic: latency constraints only apply between ChannelIn and ChannelOut blocks.
  • Added support for Verilog HDL implementation
  • Removed architecture versus implementation information
  • Removed SynthesisInfo block WYSIWYG option
  • Removed the following design examples:
    • 1K floating-point FFT
    • Radix-2 streaming FFT
    • Radix-4 streaming FFT



  • Added step about disabling virtual pins in the Quartus Prime software when using HIL with advanced blockset designs
  • Added information on _mmap.h file, which contains register information on your design
  • Corrected Has read enable and Show read enable descriptions in BusStimulus and BusStimulusFileReader blocks
  • Added BusStimulus and BusStimulusFileReader blocks to memory-mapped registers design example.
  • Added AvalonMMSlaveSettings block and DSP Builder > Avalon Interfaces > Avalon-MM slave menu option
  • Removed bus parameters from Control and Signal blocks
  • Removed the following design examples:
    • Color Space Converter (Resource Sharing Folding)
    • Interpolating FIR Filter with Updating Coefficients
    • Primitive FIR Filter (Resource Sharing Folding)
    • Single-Stage IIR Filter (Resource Sharing Folding)
    • Three-stage IIR Filter (Resource Sharing Folding)
    • Added system-in-the-loop support
  • Added new blocks:
    • Floating-point classifier
    • Floating-point multiply accumulate
    • Added hypotenuse function to math block
  • Added design examples:
    • Color space converter
    • Complex FIR design example
    • CORDIC from Primitive Blocks
    • Crest factor reduction
    • Folding FIR
    • Variable Integer Rate Decimation Filter
    • Vector sort - sequential and iterative
  • Added reference designs:
    • Crest factor reduction
    • Direct RF with Synthesizable Testbench
    • Dynamic Decimation Filter
    • Reconfigurable Decimation Filter
    • Variable Integer Rate Decimation Filter
  • Changed directory structure
  • Added correct floating-point rounding for reciprocal and square root blocks.
  • Corrected signal descriptions for LoadableCounter block
  • Removed resource sharing folder
  • Added new ALU folder information:
    • Start of packet signal
    • Clock-rate mode
June 2014 14.0
  • Added new blocks:
    • Enabled Delay Line
    • Enabled Feedback Delay
    • FFT2P, FFT4P, FFT8P, FFT16P, FFT32P, and FFT64PFFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64XFFT2, FFT4, VFFT2, and VFFT4
    • General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralTwiddle
    • )Hybrid FFT (Hybrid_FFT)
    • Parallel Pipelined FFT (PFFT_Pipe)
    • Ready
  • Updated port descriptions for
    • Convert
    • Const
    • LUT
    • Reinterpretcast
  • New parameter interfaces for:
    • FFT
    • FFT_Light
    • VFFT
    • VFFT_Light
  • Added new design examples:
    • Avalon-ST Interface (Input and Output FIFO Buffer) with Backpressure
    • Avalon-ST Interface (Output FIFO Buffer) with Backpressure
    • Fixed-point maths functions
    • Fractional square root using CORDIC
    • Normalizer
    • Square root using CORDIC
    • Switchable FFT/iFFT
    • Variable-Size Fixed-Point FFT
    • Variable-Size Fixed-Point FFT without BitReverseCoreC Block
    • Variable-Size Fixed-Point iFFTVariable-Size Fixed-Point iFFT without BitReverseCoreC Block
    • Variable-Size Floating-Point FFTVariable-Size Floating-Point FFT without BitReverseCoreC Block
    • Variable-Size Floating-Point iFFTVariable-Size Floating-Point iFFT without BitReverseCoreC Block
  • Added new ready signal for ALU folding.