DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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15.6.12. Single-Cycle Latency Latch (latch_1L)

The DSP Builder latch_1 block enable signal affects the output on the following clock cycle.

These latches work for any data type, and for vector and complex numbers.

Right-click on the block and select Look Under Mask, for the structure.

The e signal is a ufix(1) enable signal. When e is high, the latch_1 block delays data from input d by one cycle and feeds through to output q. When e is low, the latch_1 block holds the last output.

A switch in e means the latch_1 block holds the output one cycle later.