DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.8.9. Sequential Loops

This design example nests two inner loops (InnerLoopA and InnerLoopB) within the outer loop. The design example daisy chains the ld port of InnerLoopA to the ls port of InnerLoopB rather than connecting it directly to the bd port of OuterLoop. Thus each activation of InnerLoopA is followed by an activation of InnerLoopB

The model file is forloop_seqloop.mdl.