DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.8.4. Parallel Loops

This design example has two inner loops nested within the outer loop. The inner loops execute in parallel rather than sequentially. The two inner loops are started simultaneously by duplicating the control token but finish at different times. The Rendezvous block waits until both of them finish and then passes the control token back to the outer loop.

The model file is forloop_parloop.mdl.