DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.2.3. IFFT

This design example implements a 2,048 point, radix 22 iFFT. This design example accepts natural order data at the input and produces natural order data at the output. The design example includes a BitReverseCoreC block, which converts the input data stream from natural order to bit-reversed order, and an FFT block, which performs an FFT on bit-reversed data and produces its output in natural order.

Note: The FFT designs do not inherit the width in bits and scaling information. The design example specifies these values with the Wordlength and FractionLength variables in the setup script, which are 16 and 19 for this design example. To set the maximum width in bits, set the MaxOut variable. Most applications do not need the maximum width in bits. To save resources, set a threshold value for this variable. The default value of inf allows worst case bit growth.

The model file is demo_ifft.mdl.