DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.4.14. Interpolating FIR Filter with Updating Coefficient Banks

This design example is similar to the Interpolating FIR Filter with Multiple Coefficient Banks design example. While one bank is in use DSP Builder writes a new set of FIR filter coefficients to the other bank. You can see the resulting change in the filter output when the bank select switches to the updated bank.

Write to the bus interface using the BusStimulus block with a sample rate proportionate with the bus clock. Generally, DSP Builder does not guarantee bus interface transactions to be cycle accurate in Simulink simulations. However, in this design example, DSP Builder updates the coefficient bank while it is not in use.

The model name is demo_firi_updatecoeff.mdl.