DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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15.4.30. ForLoop

The ForLoop block extends the basic loop, providing a more flexible structure that implements all common loop structures—for example, triangular loops, parallel loops, and sequential loops.

Each ForLoop block manages a single counter with a token-passing scheme that allows you to link these counters in a variety ways.

Each ForLoop block has a static loop test parameter, which may be <=, <, > or >=. Loops that count up should use <= or <, depending on whether you consider the limit value, supplied by the limit signal, is within the range of the loop. Loops that count down should use >= or >.

The latency of the ForLoop block is non-zero. At loop end detection there are some cycles that may be invalid overhead required to build nested loop structures. The second activation of an inner loop does not necessarily begin immediately after the end of the first activation.

Table 202.  Port Interface for the ForLoop Block
Signal Direction Type Description Vector Data Support Complex Data Support
bs Output Boolean Token-passing inputs and outputs. The four signals ls (loop start), bs (body start), bd (body done) and ld (loop done) pass a control token between different ForLoop blocks, to create a variety of different control structures.

When the ls port receives a token, the ForLoop block initializes. The loop counter is set to its initial value (that the i signal specifies). When the bd port receives a token, the step value (s) increments the loop counter. In either case, the new value of the counter is compared with the limit value (l) with the statically-configured loop test.

If the loop test passes, the ForLoop block outputs the control token on the bs port to initiate the loop body and the valid signal, v, becomes active. If the loop test fails, the ForLoop block outputs the control token on ld port to indicate that the loop is complete and v becomes inactive.

The ForLoop block becomes active when it receives a token on its ls port, and remains active until it finally outputs a token on its ld port. Changing any of the loop parameterization inputs (i, s, or l) while the loop is active, is not supported and produces unpredictable results.

Yes No
bd Input Boolean Yes No
ld Output Boolean Yes No
ls Input Boolean Yes No
c Output Derived unsigned fixed-point type The signal c is the count output from the loop. Its value is reliable only when the valid signal, v, is active Yes No
e Input Boolean Use the enable input, e, to suspend and resume operation of the ForLoop block. When you disable the loop, the valid signal, v, goes low but DSP Builder makes no changes to the internal state of the block. When you re-enable the block, it resumes counting from the state at which you suspended it. Yes No
i Input Any unsigned fixed-point type Loop parameterization inputs. The signals i, s, and l set the initial value, step and limit value (respectively) of the loop. Use with the loop test parameter, to control the operation of the loop. The loop parameter signals must be held constant while the loop is active, but you may them when the loop is inactive. Different activations of a ForLoop block can have different start or end points, which is useful for creating nested triangular loops, for example. Yes No
s Input Any unsigned fixed-point type Yes No
l Input Any unsigned fixed-point type Yes No
el Output Boolean Auxiliary loop outputs: the signals fl and ll are active on the first loop iteration and last loop iteration, respectively. The signal el is active when the ForLoop block is processing an empty loop. Yes No
fl Output Boolean Yes No
ll Output Boolean Yes No