DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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14.1.2. Bus Stimulus (BusStimulus)

The DSP Builder Bus StimulusFileReader block with the BusStimulus block simulates accesses over the processor interface in the Simulink environment.

The BusStimulus block performs hidden accesses to the registers and SharedMem blocks in the memory hierarchy of your model. It is an interface that allows another block to read and write to any address. The address and data ports act as though an external processor reads and writes to your system.

The BusStimulus block transmits data from its input ports (address, writedata and write) over the processor interface, and thus modifies the internal state of the memory-mapped registers and memories as appropriate. Any response from the simulated processor interface is output on the readdata and readvalid output ports.

For example, to use the BusStimulus block connect constants to the address and data inputs. A pulse on the write port then writes the data to any register mapped to the specified address. Put a counter on the address input to provide all the data in every memory location on the readdata port. DSP Builder asserts the readdatavalid output when a valid read data is on the readdata port.

Table 67.  Parameters for the BusStimulus Block
Parameter Description
Sample Time Specifies the Simulink sample time.
Show read enable Turn on to show read enable port. If you use the BusStimulus with the BusStimulusFileReader blocks in a design, ensure this parameter is turned on or turned off in both blocks.
Table 68.  Port Interface for the BusStimulus Block
Signal Direction Type Description
address Input Unsigned integer Address to access.
writedata Input 16-, 32-, or 64-bit unsigned integer Write data.
write Input Boolean Write enable.
read Input Boolean Read enable.
readdata Output 16-, 32-, or 64-bit unsigned integer Read data.
readdatavalid Output Boolean Read data valid.

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