DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.13.15. Loadable Counter

This design example demonstrates the LoadableCounter block.

The testbench reloads the counter with new parameters every 64 cycles. A manual switch allows you to control whether the counter is permanently enabled, or only enabled on alternate cycles. You can view the signals input and output from the counter with the provided scope.

The model file is demo_ld_counter.mdl.