DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022
Public

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Document Table of Contents

7.9.1. Performing a Cosimulation

This tutorial uses the DSP Builder HDL import design example.

The design example has two HDL entities: the DPD (lut_dpd.vhd) and the FIR (complex_fir.vhd).

In DSP Builder cosimulation, each HDL Import block represents an HDL instance. You must instantiate both of these entities in a top-level VHDL file. For this design example, Intel provides top.vhd.

In addition, the FIR filter uses a signed data type with a generic for the data width. When DSP Builder instantiates the FIR filter, it uses its own paradigm (i.e. std_logic_vector and no generics). This design example adds a wrapper entity: complex_fir_wrapper.vhd. This entity instantiates complex_fir, including setting the generic to the appropriate value, and converts signed to std_logic_vector.

These two files, top.vhd and complex_fir_wrapper.vhd are in the to_import directory.

Procedure

  1. Add a HDL Import Config block to the top-level design.
    Figure 69. Top-level Design with HDL Import Config Block
  2. Parameterize the HDL Import Config block.
    1. Click Add to add all of the files from the to_import directory.
      The order of the files does not matter. DSP Builder determines the type of HDL file by the extension, but you can change the type manually.
    2. Enter top in the Top level instance.
    3. Turn on Top-level is a wrapper.
    4. Click the Compile button.
    5. Set the Simulink sample time field to 1.
    6. When the status light is green, click Launch Cosim.
    Figure 70. HDL Import Configuration
  3. Add a HDL Import block to the digital_up_converter subsystem.
    1. Double click the HDL Import block
    2. Click Instance and select inst_fir.
    3. Set the fractional bits of the two output signals to 16.
      Figure 71. HDL Import Block inst_fir Parameters
  4. Add a second HDL Import block to the digital_up_converter subsystem.
    1. Double click the HDL Import block
    2. Click Instance and select inst_dpd.
    3. Set the fractional bits of the two output signals to 27.
    4. Set the valid output to unsigned.
    Figure 72. HDL Import inst_dpd Parameters
  5. Wire up HDL import blocks.
    The HDL Import block port names are in alphabetical order.
    Figure 73. Wire up HDL Import Blocks
  6. Press the play button or advance through the simulation a cycle at a time.
  7. Verify HDL import with the ModelSim simulator, in DSP Builder, select DSP Builder > Run ModelSim > Device.
    The cosimulation turns any non-high state (e.g. U or X) to a zero.
  8. Compile the design in Intel® Quartus® Prime, by selecting DSP Builder > Run Quartus Prime Software.