Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

3.1. Features

The Arria® V variable precision DSP blocks offer the following features:

  • High-performance, power-optimized, and fully registered multiplication operations
  • 9-bit, 18-bit, 27-bit, and 36-bit 2 word lengths
  • 18 x 19 and 18 x 25 complex multiplications 2
  • Built-in addition, subtraction, and 64-bit accumulation unit to combine multiplication results
  • Cascading 19-bit or 27-bit to form the tap-delay line for filtering applications
  • Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
  • Hard pre-adder supported in 18-bit , 19-bit, and 27-bit mode for symmetric filters
  • Internal coefficient register bank for filter implementation
  • 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
2 Only applicable for certain device variant. Refer to Supported Operational Modes in Arria V Devices for details.