7.4.5. PHY Clock (PHYCLK) Networks
The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a high-performance external memory interface.
The top and bottom sides of the Arria® V devices have up to four PHYCLK networks. There are up to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank and is driven by one of the PLLs located adjacent to the I/O bank.
The following figures show the PHYCLK networks available in the Arria® V devices.
The PHYCLK network can be used to drive I/O sub-banks in each I/O bank. Each I/O sub-bank can be driven by only one PHYCLK network—all I/O pins in an I/O sub-bank are driven by the same PHYCLK network.
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