Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

7.4.5. PHY Clock (PHYCLK) Networks

The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a high-performance external memory interface.

The top and bottom sides of the Arria® V devices have up to four PHYCLK networks. There are up to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank and is driven by one of the PLLs located adjacent to the I/O bank.

The following figures show the PHYCLK networks available in the Arria® V devices.

Figure 166. PHYCLK Networks in Arria® V GX A1 and A3 Devices

Figure 167. PHYCLK Networks in Arria® V GX A5, A7, B1, B3, B5, and B7 Devices, and Arria® V GZ E1, E3, E5, and E7 Devices

Figure 168.  Arria® V PHYCLK Networks in Arria® V SX B3 and B5 Devices, and Arria® V ST D3 and D5 Devices

The PHYCLK network can be used to drive I/O sub-banks in each I/O bank. Each I/O sub-bank can be driven by only one PHYCLK network—all I/O pins in an I/O sub-bank are driven by the same PHYCLK network.