Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

8.1. Enhanced Configuration and Configuration via Protocol

Table 93.  Configuration Schemes and Features of Arria® V Devices Arria® V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V 25 programming voltages and several configuration schemes.
Mode Data Width Max Clock Rate (MHz) Max Data Rate (Mbps) Decompression Design Security Remote System Update
AS through the EPCS and EPCQ serial configuration device 1 bit, 4 bits 100 Yes Yes Yes
PS through CPLD or external microcontroller 1 bit 125 125 Yes Yes
FPP 8 bits 125 Yes Yes Parallel flash loader
16 bits 125 Yes Yes
32 bits26 100 Yes Yes
CvP (PCIe) x1, x2, x4, and x8 lanes Yes Yes
JTAG 1 bit 33 33
Configuration via HPS 16 bits 125 Yes Yes Parallel flash loader
32 bits 100 Yes Yes

Instead of using an external flash or ROM, you can configure the Arria® V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Arria® V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

Note: Although Arria® V GZ devices support PCIe Gen3, you can use only PCIe Gen1 and PCIe Gen2 for CvP configuration scheme.
25 Arria® V GZ does not support 3.3 V.
26 Arria® V GZ only