Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

7.5.1. Features of the Hard Memory Controller

Table 87.  Features of the Arria V Hard Memory Controller



Memory Interface Data Width

  • 8, 16, and 32 bit data
  • 16 bit data + 8 bit ECC
  • 32 bit data + 8bit ECC

Memory Density

The controller supports up to four gigabits density parts and two chip selects.

Memory Burst Length

  • DDR3—Burst length of 8 and burst chop of 4
  • DDR2—Burst lengths of 4 and 8

Command and Data Reordering

The controller increases efficiency through the support for out-of-order execution of DRAM commands—with address collision detection-and in-order return of results.

Starvation Control

A starvation counter ensures that all requests are served after a predefined time-out period. This function ensures that data with low priority access are not left behind when reordering data for efficiency.

User-Configurable Priority Support

When the controller detects a high priority request, it allows the request to bypass the current queuing request. This request is processed immediately and thus reduces latency.

Avalon®-MM Data Slave Local Interface

By default, the controller supports the Avalon Memory-Mapped protocol.

Bank Management

By default, the controller provides closed-page bank management on every access. The controller intelligently keeps a row open based on incoming traffic. This feature improves the efficiency of the controller especially for random traffic.

Streaming Reads and Writes

The controller can issue reads or writes continuously to sequential addresses every clock cycle if the bank is open. This function allows for very high efficiencies with large amounts of data.

Bank Interleaving

The controller can issue reads or writes continuously to 'random' addresses.

Predictive Bank Management

The controller can issue bank management commands early so that the correct row is open when the read or write occurs. This increases efficiency.

Multiport Interface

The interface allows you to connect up to six data masters to access the memory controller through the local interface. You can update the multiport scheduling configuration without interrupting traffic on a port.

Built-in Burst Adaptor

The controller can accept bursts of arbitrary sizes on its local interface and map these bursts to efficient memory commands.

Run-time Configuration of the Controller

This feature provides support for updates to the timing parameters without requiring reconfiguration of the FPGA, apart from the standard compile-time setting of the timing parameters.

On-Die Termination

The controller controls the on-die termination (ODT) in the memory, which improves signal integrity and simplifies your board design.

User-Controlled Refresh Timing

You can optionally control when refreshes occur—allowing the refreshes to avoid clashing of important reads or writes with the refresh lock-out time.

Low Power Modes

You can optionally request the controller to put the memory into the self-refresh or deep power-down modes.

Partial Array Self-Refresh

You can select the region of memory to refresh during self-refresh through the mode register to save power.


Standard Hamming single error correction, double error detection (SECDED) error correction code (ECC) support:

  • 32 bit data + 8 bit ECC
  • 16 bit data + 8 bit ECC

Additive Latency

With additive latency, the controller can issue a READ/WRITE command after the ACTIVATE command to the bank prior to t RCD to increase the command efficiency.

Efficiency degradation may occur when using the additive latency feature with the hard memory controller for DDR3 SDRAM interfaces at 533 MHz.

Write Acknowledgment

The controller supports write acknowledgment on the local interface.

User Control of Memory Controller Initialization

The controller supports initialization of the memory controller under the control of user logic—for example, through the software control in the user system if a processor is present.

Controller Bonding Support

You can bond two controllers to achieve wider data width for higher bandwidth applications.