Arria V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 7/24/2020
Document Table of Contents

6.2.3. Pin Placement Guidelines for DPA and Non-DPA Differential Channels

DPA usage adds some constraints on the placement of high-speed differential channels. If DPA-enabled or DPA-disabled differential channels22 in the differential banks are used, you must adhere to the differential pin placement guidelines to ensure the proper high-speed operation. The Intel® Quartus® Prime compiler automatically checks the design and issues an error message if the guidelines are not followed.

Note: The figures in this section show guidelines for using corner and center PLLs but do not necessarily represent the exact locations of the high-speed LVDS I/O banks.
22 DPA-enabled differential channels refer to DPA mode or soft-CDR mode while DPA disabled channels refer to non-DPA mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message