Arria V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 7/24/2020
Document Table of Contents 27-Bit Systolic FIR Mode

In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of 1,024 multiplier products.

The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block.

Figure 61.  27-Bit Systolic FIR Mode for Arria V GX, GT, SX, and ST Devices

Figure 62.  27-Bit Systolic FIR Mode for Arria V GZ Devices

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