Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

8.14. Configuration, Design Security, and Remote System Upgrades in Arria V Devices Revision History

Document Version Changes
2023.10.18 Updated the notes in Security Modes for clarity.
2020.07.24 Added topic: I/O Standards and Drive Strength for Configuration Pins.
  • Removed topic: I/O Standards and Drive Strength for Configuration Pins.
  • Updated the User Mode topic.
2019.10.03 Added a note to Device Configuration Pins to state that the DCLK, AS_DATA0/ASDO, AS_DATA1, AS_DATA2, AS_DATA3, and nCSO pins have 25 kOhm pull-up resistors when the MSEL pins are set to AS configuration scheme.
  • Updated the Active Serial Configuration topic.
  • Updated Figure: AS Configuration Timing Waveform.
Date Version Changes
December 2017 2017.12.15 Added description in the I/O Standards and Drive Strength for Configuration Pins table.
December 2016 2016.12.09 Changed the term "configuration mode" to "configuration scheme" when referring to a configuration scheme.
August 2016 2016.08.24 Added note to Power Up and Reset states in the Configuration Sequence for Cyclone V Devices diagram.
June 2016 2016.06.10
  • Added a note to specify the time between nCSO falling edge to first toggle of DCLK is more than 15ns in AS Configuration Timing figure.
December 2015 2015.12.21
  • Changed instances of Quartus II to Quartus Prime.
  • Added the CvP_CONFDONE pin to the Configuration Pin Summary for Arria V Devices table.
  • Added the I/O Standards and Drive Strength for Configuration Pins table.
June 2015 2015.06.12
  • Added timing waveforms for FPP, AS, and PS configuration.
  • Updated the Trace Length and Loading Guideline section.
January 2015 2015.01.23
  • Added the Transmitting Configuration Data section.
  • Updated the Configuration Images section.
June 2014 2014.06.30
  • Updated Figure 8-17: JTAG Configuration of a Single Device Using a Download Cable.
  • Updated Figure 8-19: JTAG Configuration of Multiple Devices Using a Download Cable.
  • Updated the maximum clock rate for Partial Reconfiguration in Table 8-1.
  • Updated the MSEL pin settings recommendation in the MSEL Pin Settings section.
January 2014 2014.01.10
  • Added a link to the FPGA Manager chapter for details about the MSEL pin settings for the HPS in SoC FPGA devices.
  • Updated the VCCPD Pin section.
  • Updated the Enabling Remote System Upgrade Circuitry section.
  • Updated the Configuration Pin Summary section.
  • Updated Figure 8-3, Figure 8-7, and Figure 8-14.
June 2013 2013.06.11 Updated the Configuration Error Handling section.
May 2013 2013.05.10 Removed support for active serial multi-device configuration using the same configuration data.
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Added the ALTCHIP_ID megafunction section.
  • Updated "Connection Setup for Programming the EPCS Using the JTAG Interface" and "Connection Setup for Programming the EPCQ Using the JTAG Interface" figures.
  • Added the nIO_PULLUP pin in Table 8-3: Configuration Pin Summary for Arria® V Devices.
  • Added links for AS, PS, FPP, and JTAG configuration timing to device datasheet.
  • Moved all links to the Related Information section of respective topics for easy reference.
November 2012 2012.11.19
  • Added configuration modes and features for Arria® V devices.
  • Added FPP x32 for Arria® V GZ devices.
  • Added DATA[31..16] for Arria® V GZ devices.
  • Reorganized content and updated template.
June 2012 2.0 Restructured the chapter.
November 2011 1.1 Minor text edits.
October 2011 1.0 Initial release.