Visible to Intel only — GUID: sam1403478298618
Ixiasoft
Visible to Intel only — GUID: sam1403478298618
Ixiasoft
6.4.2.2. DPA Mode
The DPA block chooses the best possible clock (DPA_diffioclk) from the eight fast clocks that the fractional PLL sent. This serial DPA_diffioclk clock is used for writing the serial data into the synchronizer. A serial LVDS_diffioclk clock is used for reading the serial data from the synchronizer. The same LVDS_diffioclk clock is used in data realignment and deserializer blocks.
The following figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.
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