Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents DPA Mode

The DPA block chooses the best possible clock (DPA_diffioclk) from the eight fast clocks that the fractional PLL sent. This serial DPA_diffioclk clock is used for writing the serial data into the synchronizer. A serial LVDS_diffioclk clock is used for reading the serial data from the synchronizer. The same LVDS_diffioclk clock is used in data realignment and deserializer blocks.

The following figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.

Figure 152. Receiver Datapath in DPA Mode In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.