Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

7.6. External Memory Interfaces in Arria V Devices Revision History

Date Version Changes
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2015 2015.01.23
  • Updated hard memory controller widths for all devices.
  • Removed "Preliminary" notes.
June 2014 2014.06.30
  • Added links to the Arria® V Device Overview for more information about which device feature option supports the hard memory controllers.
  • Updated the hard memory controller widths for all devices where the widths are 64, 72, and 80 bits. The widths are now updated to "32 + 32", "40 + 32", and "40 + 40", respectively. The update is to clarify the maximum interface width per hard memory controller in the devices.
January 2014 2014.01.10
  • Reduced the soft memory controller performance for DDR3 1.35 V in Arria® V GX, GT, SX, and ST devices from 667 MHz to 600 MHz.
  • Removed support for DDR2 in the HPS hard memory controller.
  • Updated the figure that shows the delay chains in the Arria® V GZ I/O block.
  • Added related information link to ALTDQ_DQS2 Megafunction User Guide for more information about using the delay chains.
  • Changed all "SoC FPGA" to "SoC".
  • Updated the figure that shows the DQS/CQ/CQn/QK# Pins and DLLs in Arria® V GX A1 and A3 to add the DLL reference clock to the left side DLL.
  • Updated the topic about delay-locked loop (DLL) to specify that there is a maximum of five DLLs (instead of four).
  • Updated the topic about the PHYCLK networks to add information about using the PHYCLK network to drive the I/O sub-banks in each I/O bank.
  • Added links to Altera's External Memory Spec Estimator tool to the topics listing the external memory interface performance.
  • Updated topic about hard memory controller bonding support to specify that bonding is supported only for hard memory controllers configured with one port.
May 2013 2013.05.06
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Added link to the known document issues in the Knowledge Base.
  • Updated the topic about Arria V GZ leveling circuitry.
  • Removed the Arria V GZ phase offset control topic.
  • Added the I/O and DQS configuration blocks topic.
  • Updated the DQ/DQS groups for Arria V GX.
  • Added the DQ/DQS groups for Arria V GT C3 and C7.
  • Added the DLL reference clock input tables for all Arria V devices.
  • Added the FPGA hard memory controller widths for Arria V GX, GT, SX, and ST.
  • Added the HPS hard memory controller widths for Arria V SX and ST.
November 2012 2012.11.19
  • Reorganized content and updated template.
  • Added information for Arria V GZ, including a topic on the leveling circuitry.
  • Added a list of supported external memory interface standards using the hard memory controller and soft memory controller.
  • Added performance information for external memory interfaces and the HPS external memory interfaces.
  • Separated the DQ/DQS groups tables into separate topics for each device variant for easy reference.
  • Moved the PHYCLK networks pin placement guideline to the Planning Pin and FPGA Resources chapter of the External Memory Interface Handbook.
  • Moved information from the "Design Considerations" section into relevant topics.
  • Removed the "DDR2 SDRAM Interface" and "DDR3 SDRAM DIMM" sections. Refer to the relevant sections in the External Memory Interface Handbook for the information.
  • Updated the diagram for DQS/CQ/CQn/QK# pins and DLLs in Arria V GX A1 and A3 devices to add DLLs on the right, top left, and bottom left, and update the DLL connections to the pins.
  • Updated the term "Multiport logic" to "multi-port front end" (MPFE).
June 2012 2.0

Updated for the Quartus II software v12.0 release:

  • Restructured chapter.
  • Updated “Design Considerations”, “DQS Postamble Circuitry”, and “IOE Registers”sections.
  • Added SoC devices information.
  • Added Figure 7–4, Figure 7–8, and Figure 7–20.
November 2011 1.1
  • Updated Table 7–2.
  • Added “PHY Clock (PHYCLK) Networks” and “UniPHY IP” sections.
  • Restructured chapter.
May 2011 1.0

Initial release.