Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

7.3.1. Guideline: Using DQ/DQS Pins

The following list provides guidelines on using the DQ/DQS pins:

  • The devices support DQ and DQS signals with DQ bus modes of x4/x8/x9, x16/x18, or x32/x36.
  • You can use the DQSn or CQn pins that are not used for clocking as DQ pins.
  • If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os. However, unused HPS DQ/DQS pins on the Arria® V SX and ST devices cannot be used as user I/Os.
  • Some pins have multiple functions such as RZQ or DQ. If you need extra RZQ pins, you can use some of the DQ pins as RZQ pins instead.
Note: For the x8, x16/x18, or x32/x36 DQ/DQS groups whose members are used as RZQ pins, Altera recommends that you assign the DQ and DQS pins manually. Otherwise, the Intel® Quartus® Prime software might not be able to place the DQ and DQS pins, resulting in a “no-fit” error.

Reading the Pin Table

For the maximum number of DQ pins and the exact number per group for a particular Arria® V device, refer to the relevant device pin table.

In the pin tables, the DQS and DQSn pins denote the differential data strobe/clock pin pairs, while the CQ and CQn pins denote the complementary echo clock signals. The pin table lists the parity, DM, BWSn, NWSn, ECC, and QVLD pins as DQ pins.