Arria V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 7/24/2020
Document Table of Contents

4. Clock Networks and PLLs in Arria V Devices

This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs) in Arria® V devices. The Intel® Quartus® Prime software enables the PLLs and their features without external devices.

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