Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
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8.5. Device Configuration Pins

Configuration Pins Summary

The following table lists the Arria® V configuration pins and their power supply.

Note:
  1. The TDI, TMS, TCK, and TDO pins are powered by VCCPD of the bank in which the pin resides.
  2. The CLKUSR, DEV_OE , DEV_CLRn , DATA[15..5] , and DATA[31..16] pins are powered by VCCPGM during configuration and by VCCIO of the bank in which the pin resides if you use it as a user I/O pin.
  3. The DCLK, AS_DATA0/ASDO, AS_DATA1, AS_DATA2, AS_DATA3, and nCSO pins have 25 kOhm pull-up resistors when the MSEL pins are set to AS configuration scheme.
Table 95.  Configuration Pin Summary for Arria V Devices
Configuration Pin Configuration Scheme Input/Output User Mode Powered By
TDI JTAG Input VCCPD
TMS JTAG Input VCCPD
TCK JTAG Input VCCPD
TDO JTAG Output VCCPD
CLKUSR All schemes Input I/O VCCPGM /VCCIO 29
CRC_ERROR Optional, all schemes Output I/O Pull-up
CONF_DONE All schemes Bidirectional VCCPGM /Pull-up
DCLK FPP and PS Input VCCPGM
AS Output VCCPGM
DEV_OE Optional, all schemes Input I/O VCCPGM /VCCIO 29
DEV_CLRn Optional, all schemes   I/O VCCPGM /VCCIO 29
INIT_DONE Optional, all schemes Output I/O Pull-up
MSEL[4..0] All schemes Input VCCPGM
nSTATUS All schemes Bidirectional VCCPGM /Pull-up
nCE All schemes Input VCCPGM
nCEO All schemes Output I/O Pull-up
nCONFIG All schemes Input VCCPGM
nIO_PULLUP 30 All schemes Input VCCPGM
DATA[15..5] FPP x8 and x16 Input I/O VCCPGM /VCCIO 29
DATA[31..16] 30 FPP x32 Input I/O VCCPGM /VCCIO 29
DATA[4..0] 30 FPP x8, x16, and x32 Input I/O VCCPGM /VCCIO 29
nCSO/DATA4 31 AS Output VCCPGM
FPP Input VCCPGM
AS_DATA[3..1] / DATA[3..1] 31 AS Bidirectional VCCPGM
FPP Input VCCPGM
AS_DATA0 / DATA0 /ASDO 31 AS Bidirectional VCCPGM
FPP and PS Input VCCPGM
AS_DATA0/ASDO 30 AS Bidirectional VCCPGM
AS_DATA[3..1] 30 AS Bidirectional VCCPGM
PR_REQUEST Partial Reconfiguration Input I/O VCCPGM /VCCIO 29
PR_READY Partial Reconfiguration Output I/O VCCPGM /VCCIO 29
PR_ERROR Partial Reconfiguration Output I/O VCCPGM /VCCIO 29
PR_DONE Partial Reconfiguration Output I/O VCCPGM /VCCIO 29
CvP_CONFDONE CvP (PCIe) Output I/O VCCPGM /VCCIO 29
29 This pin is powered by VCCPGM during configuration and powered by VCCIO of the bank in which the pin resides when you use this pin as a user I/O pin.
30 These pins are applicable for Arria® V GZ devices only.
31 These pins are applicable for all Arria® V devices except for Arria® V GZ devices.