Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

3.5.8. Double Accumulation Register

The double accumulation register is an extra register in the feedback path of the accumulator. Enabling the double accumulation register will cause an extra clock cycle delay in the feedback path of the accumulator.

This register has the same CLK, ENA, and ACLR settings as the output register bank.

By enabling this register, you can have two accumulator channels using the same number of variable precision DSP block.

Double accumulation register is not available in Arria® V GZ devices.