Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

6.6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices Revision History

Date Version Changes
December 2017 2017.12.15
  • Added a note to Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only topic to clarify that spread-spectrum input clock is not supported in LVDS.
  • Updated for latest Intel branding standards.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.08
  • Changed figure title "Corner PLLs Driving DPA-enabled Differential I/Os" to "Invalid Usage of Corner PLLs Driving DPA-enabled Differential I/Os".
  • Added LVDS and DPA Clock Network figure in Guideline: Using DPA-Enabled Differential Channels.
  • Updated all figures in Guideline: Using DPA-Enabled Differential Channels.
  • Updated guidelines for using both corner PLLs in Arria V Devices.
  • Updated figures in Guideline: Using DPA-Disabled LVDS Differential Channels.
  • Updated the statement about emulated LVDS buffers to specify that you can use true LVDS input buffer as emulated output buffers for serialization factor of 1 and 2.
January 2015 2015.01.19
  • Removed statement on explanation related to rx_synclock for figure "LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode)".
  • Updated figure LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode) and figure Receiver Datapath in Soft-CDR Mode.
  • Added a note to leave rx_enable and rx_inclock to be unconnected for figure LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode).
  • Updated timing diagram for Phase Relationship for External PLL Interface Signals to reflect the correct phase shift and frequency for outclk2.
January 2014 2014.01.10
  • Updated the statement about setting the phase of the clock in relation to data in the topic about transmitter clocking.
  • Added a figure that shows the phase relationship for the external PLL interface signals.
  • Clarified that "one row of separation" between two groups of DPA-enabled channels means a separation of one differential channel.
  • Clarified that "internal PLL option" refers to the option in the ALTLVDS megafunction.
  • Updated the topic about emulated LVDS buffers to clarify that you can use unutilized true LVDS input channels (instead "buffers") as emulated LVDS output buffers.
August 2013 2013.08.19

Updated the number of LVDS channels of the Arria V GZ E5 and E7 devices (1517-pin package) from 80 to 79 (top banks TX) and 82 to 81 (top banks RX).

June 2013 2013.06.21

Updated the figure about data realignment timing to correct the data pattern after a bit slip.

May 2013 2013.05.06
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Added link to the known document issues in the Knowledge Base.
  • Clarified that the clock tree network cannot cross over to different I/O regions only applies to Arria V GZ.
  • Added a figure to show the center PLLs driving the DPA-enabled differential I/Os in Arria V GZ devices.
  • Changed the color of the transceiver blocks in the high-speed differential I/O location diagrams for clarity.
  • Reorganized contents under the differential receiver topic.
  • Added a topic about emulated LVDS buffers.
  • Edited the topic about true LVDS buffers.
  • Corrected references to upper and lower I/O banks to left and right I/O banks, respectively.
  • Updated the data realignment timing figure to improve clarity.
  • Updated the receiver data realignment rollover figure to improve clarity.
November 2012 2012.11.19
  • Reorganized content and updated template.
  • Added Arria V GZ information.
  • Added Altera_PLL settings for external PLL usage in DPA and non-DPA modes.
  • Updated clocking examples. Altera_PLL now supports entering negative phase shift.
  • Rearranged the LVDS channel counts table into several tables according to device variant for ease of reference.
  • Updated the Arria V GX A1 and A3 LVDS channel counts, and added the channel counts for Arria V GZ.
  • Removed references to ALTPLL and added information about Altera_PLL. Altera_PLL now replaces ALTPLL for Arria V devices.
  • Added design guidelines for using LVDS interface with the external PLL mode. These include information on the signal interfaces, the parameter values, and the connection between Altera_PLL and ALTLVDS in external PLL mode.
  • Updated the programmable VOD allowed values for Arria V GX, GT, SX, and ST, and added the values for Arria V GZ.
  • Moved the PLL and clocking section into design guideline topics.
  • Added steps to assign input delay to LVDS receiver using the TimeQuest Timing Analyzer.
June 2012 2.0
  • Restructured the chapter.
  • Updated Table 6–1.
  • Updated Figure 6–1 and Figure 6–2.
  • Added Figure 6–3.
  • Added “Design Considerations” section.
  • Updated the “Differential Pin Placement” section.
November 2011 1.1
  • Updated Table 6–1.
  • Restructured chapter.
May 2011 1.0 Initial release.