Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

7.4. External Memory Interface Features in Arria V Devices

The Arria® V I/O elements (IOE) provide built-in functionality required for a rapid and robust implementation of external memory interfacing.

The following device features are available for external memory interfaces:

  • DQS phase-shift circuitry
  • PHY Clock (PHYCLK) networks
  • DQS logic block
  • Dynamic on-chip termination (OCT) control
  • IOE registers
  • Delay chains
  • Hard memory controllers (Arria V GX, GT, SX, and ST only)
  • Read- and write-leveling support (Arria V GZ only)