Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Public
Document Table of Contents

7.4.9.2. Output Registers

The Arria® V output and output-enable path is divided into the HDR block, and output and output-enable registers. The device can bypass each block of the output and output-enable path.

The output path is designed to route combinatorial or registered single data rate (SDR) outputs and full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted to full-rate with the HDR block, clocked by the half-rate clock from the PLL.

The output-enable path has a structure similar to the output path—ensuring that the output-enable path goes through the same delay and latency as the output path.

Figure 177. IOE Output and Output-Enable Path Registers for Arria V GX, GT, SX, and ST Devices The following figure shows the registers available in the Arria® V GX, GT, SX, and ST output and output-enable paths.


Figure 178. IOE Output and Output-Enable Path Registers for Arria® V GZ Devices The following figure shows the registers available in the Arria® V GZ output and output-enable paths. You can bypass each register block of the output and output-enable paths.