Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

5.11. I/O Features in Arria V Devices Revision History

Document Version Changes
2018.08.09 Updated the note in Dynamic OCT in Arria V Devices topic.
Date Version Changes
June 2016 2016.06.10
  • Clarified the example quoted in Non-Voltage-Referenced I/O Standards can support 2.5 V, 3.0 V and 3.3 V inputs.
December 2015 2015.12.21
  • Added assignment name and supported I/O standards in Summary of Supported Programmable IOE Features and Settings Table.
  • Changed instances of Quartus II to Quartus Prime.
January 215 2015.01.23
  • Corrected truncated sentence in the note about the recommendation to use dynamic OCT for several I/O standards with DDR3 external memory interface.
  • Added pin placement guidelines for general purpose high-speed signals faster than 200 MHz.
  • Added 3.3V to Arria V I/O Standards Voltage Levels table for 3.3V LVTTL/3.3V LVCMOS, 3.0V LVTTL/3.0V LVCMOS and 2.5V LVCMOS I/O Standard.
  • Clarified that dedicated configuration pins, clock pins and JTAG pins do not support programmable pull-up resistor but these pins have fixed value of internal pull-up resistors.
  • Moved the Open-Drain Output, Bus-Hold Circuitry and Pull-up Resistor sections to Programmable IOE Features in Arria V Devices.
  • Update Open-Drain Output section with steps to enable open-drain output in Assignment Editor.
June 2014 2014.06.30
  • Added footnote to clarify that some of the voltage levels listed in the MultiVolt I/O support table are for showing that multiple single-ended I/O standards are not compatible with certain VCCIO voltages.
  • Updated the I/O banks locations figures to match the available modular I/O banks for Arria V GX, GT, SX, and ST devices.
  • Added information to clarify that programmable output slew rate is available for single-ended and emulated LVDS I/O standards.
  • Finalized calibrated RS and RT OCT values and updated the RT OCT values for HSUL-12 and Differential HSUL-12 I/O standards.
  • Updated the VCCPD guideline to clarify that bank 7A is not available as user I/O bank. In Arria V SX and ST devices, banks 6A, 6B, and 7A through 7E are allocated for the HPS.
January 2014 2014.01.10
  • Updated statements in several topics to clarify that each modular I/O bank can support multiple I/O standards that use the same voltages.
  • Updated the guideline topic about using the same VCCPD for I/O banks in the same VCCPD group to improve clarity.
  • Added the optional PCI clamp diode to the figure showing the IOE structure.
  • Changed all "SoC FPGA" to "SoC".
  • Removed SSTL-125 from the list of supported I/O standards for the HPS I/O.
  • Removed all "preliminary" marks.
  • Removed the statement specifying that value "0" of the programmable VOD is only available for RSDS and mini-LVDS I/O standards only. The value is now available for the LVDS I/O standards.
  • Clarified that you can only use RD OCT if VCCPD is 2.5 V.
  • Added link to Knowledge Base article that clarifies about vertical migration (drop-in compatibility).
  • Corrected the modular I/O banks tables for Arria® V SX and ST devices. Bank 7G, available in the F1517 package, is an FPGA I/O bank instead of an HPS column I/O bank. The number of I/O pins remain the same.
August 2013 2013.08.19

Added 3.3 V input signal for 2.5 V VCCIO in the table listing the MultiVolt I/O support.

June 2013 2013.06.21
  • Removed 3.3 V input signal for 2.5 V VCCIO in the table listing the MultiVolt I/O support.
  • Updated the topic about LVDS input RD OCT to remove the requirement for setting the VCCIO to 2.5 V. RD OCT now requires only that the VCCPD is 2.5 V.
  • Updated the topic about LVPECL termination to improve clarity.
May 2013 2013.05.06
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Added link to the known document issues in the Knowledge Base.
  • Added note about the power-up sequence requirement if you plan to migrate your design to devices that require the specific power-up sequence.
  • Updated the RT OCT input termination settings for the 1.5 V SSTL I/O standards.
  • Updated the maximum speed of RSDS and mini-LVDS to 360 Mbps and 400 Mbps, respectively, in the notes for the supported FPGA I/O standards table.
December 2012 2012.12.04
  • Added LVVTL and LVCMOS voltage levels for the Arria V GZ variant, and corrected the LVVTL and LVCMOS voltage levels for the Arria V GX, GT, SX, and ST devices.
  • Updated the SSTL and HSTL I/O termination figures to add VREF inputs for OCT in bidirectional pins.
November 2012 2012.11.19
  • Reorganized content and updated template.
  • Added the I/O resources per package and I/O vertical migration sections for easy reference.
  • Added the steps to verify pin migration compatibility using the Quartus II software.
  • Updated the I/O standards support table with Arria V GZ and HPS I/O information.
  • Updated the guideline about mixing voltage-referenced and non-voltage-referenced I/O standards to include Arria V GZ information.
  • Updated the guideline about observing device absolute maximum rating for 3.3 V interfacing, specifically the off-chip clamping diode usage for Arria V GZ.
  • Updated the VREF pin restrictions guideline to specify that it applies only to Arria V GX, GT, SX, and ST, but not Arria V GZ.
  • Added the I/O bank locations for Arria V GZ devices.
  • Rearranged the I/O banks groups tables for easier reference.
  • Added modular I/O banks for Arria V GZ devices.
  • Restructured the information in the topic about I/O buffers and registers to improve clarity and for faster reference.
  • Added Arria V GZ and HPS information to the topic on programmable IOE features.
  • Rearranged the tables about on-chip I/O termination for clarity and topic-based reference.
  • Added Arria V GZ OCT information to all on-chip I/O termination tables.
  • Added all I/O standards and external termination schemes supported by all Arria V devices to the external I/O termination table.
June 2012 2.0

Updated for the Quartus II software v12.0 release:

  • Restructured chapter.
  • Added “Design Considerations”, “VCCIO Restriction”, “LVDS Channels”, “Modular I/O Banks”, and “OCT Calibration Block” sections.
  • Added Figure 5–1, Figure 5–2, and Figure 5–3
  • Updated Table 5–1, Table 5–6, and Table 5–8.
  • Updated Figure 5–19 with emulated LVDS with external single resistor.
February 2012 1.2 Updated Table 5–3.
November 2011 1.1
  • Restructured chapter.
  • Updated Table 5–3.
May 2011 1.0 Initial release.