Arria V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 7/24/2020
Public
Document Table of Contents

4.1.2.2. Regional Clock Networks

RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock insertion delay and skew for logic contained within a single device quadrant. The Arria® V IOEs and internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals.

Figure 64. RCLK Networks in Arria V GX, GT, SX, and ST Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Figure 65. RCLK Networks in Arria V  GZ Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


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