Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

7.4.10. Delay Chains

The Arria® V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks. You can control the delay chain setting through the I/O or the DQS configuration block output.

Every I/O block contains a delay chain between the following elements:

  • The output registers and output buffer
  • The input buffer and input register
  • The output enable and output buffer
  • The R T OCT enable-control register and output buffer
Figure 179. Delay Chains in an I/O Block in the Arria® V GX, GT, SX, and ST Devices

Figure 180. Delay Chains in an I/O Block in Arria® V GZ Devices

Each DQS logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input.

Figure 181. Delay Chains in the DQS Input Path