Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

2.11. Embedded Memory Blocks in Arria V Devices Revision History

Date Version Changes
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2015 2015.01.23
  • Reword Total RAM bits in Memory Features in Arria V Devices table to Capacity per Block.
June 2014 2014.06.30 Added information about MLAB memory blocks support for simultaneous read/write operations. MLAB memory blocks only support simultaneous read/write operations when operating in single clock mode.
May 2013 2013.05.06
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Added link to the known document issues in the Knowledge Base.
  • Corrected the description about the "don't care" output mode for RAM in mixed-port read-during-write.
  • Reorganized the structure of the supported memory configurations topics (single-port and mixed-width dual-port) to improve clarity about maximum data widths supported for each configuration.
  • Added a description to the table listing the maximum embedded memory configurations to clarify that the information applies only to the single port or ROM mode.
  • Removed the topic about mixed-width configurations for MLABs and added a note to clarify that MLABs do not support mixed-width configuration.
November 2012 2012.11.19
  • Reorganized content and updated template.
  • Added information for Arria V GZ including M20K memory, memory features, and memory capacity.
  • Added and updated memory capacity information from the Arria V Device Overview for easy reference.
  • Moved information about supported memory block configurations into its own table.
  • Added short descriptions of each clocking mode.
  • Added topic about the packed mode support.
  • Added topic about the address clock enable support.
  • Added topic about ECC support and the ECC truth table.
June 2012 2.0
  • Restructured the chapter.
  • Updated the “Memory Modes”, “Clocking Modes”, and “Design Considerations” sections.
  • Updated Table 2–1.
  • Added the “Parity Bit” and “Byte Enable” sections.
  • Moved the memory capacity information to the Arria V Device Overview.
November 2011 1.1
  • Updated Table 2–1.
  • Restructured chapter.
May 2011 1.0 Initial release.