Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Public
Document Table of Contents
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2.3. Embedded Memory Features

Table 5.  Memory Features in Arria V Devices This table summarizes the features supported by the embedded memory blocks.
Features M20K , M10K MLAB
Maximum operating frequency
  • M20K—600 MHz
  • M10K—400 MHz
  • Arria® V GX, GT, SX, and ST—500 MHz
  • Arria® V GZ—600 MHz
Capacity per block (including parity bits)
  • M20K—20,480
  • M10K—10,240

640

Parity bits Supported Supported
Byte enable Supported Supported
Packed mode Supported
Address clock enable Supported Supported
Simple dual-port mixed width Supported
True dual-port mixed width Supported
FIFO buffer mixed width Supported
Memory Initialization File (.mif) Supported Supported
Mixed-clock mode Supported Supported
Fully synchronous memory Supported Supported
Asynchronous memory Only for flow-through read memory operations.
Power-up state

Output ports are cleared.

  • Registered output ports—Cleared.
  • Unregistered output ports—Read memory contents.
Asynchronous clears Output registers and output latches Output registers and output latches
Write/read operation triggering Rising clock edges Rising clock edges
Same-port read-during-write
  • M20K—output ports set to new data
  • M10K—output ports set to "new data" or "don't care"

(The "don't care" mode applies only for the single-port RAM mode).

Output ports set to "don't care".

Mixed-port read-during-write Output ports set to "old data" or "don't care". Output ports set to "old data", "new data", "don't care", or "constrained don't care".
ECC support

Soft IP support using the Intel® Quartus® Prime software.

Built-in support in x32-wide simple dual-port mode (M20K only).

Soft IP support using the Intel® Quartus® Prime software.