Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

4.3. Clock Networks and PLLs in Arria V Devices Revision History

Document Version Changes
  • Corrected the signal name from clkswitch to extswitch.
  • Updated the description for the automatic switchover with manual override mode in the Clock Switchover section.
  • Updated the description about the extswitch signal in the Manual Clock Switchover section.
Date Version Changes
December 2016 2016.12.09 Added a note to dedicated refclk pin in Fractional PLL High-Level Block Diagram.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2015 2015.01.23
  • Added a note pointing to FRACTIONALPLL_X183_Y63 and FRACTIONALPLL_X183_Y54 in PLL locations diagram for Arria® V SX B3 and B5 Devices, and Arria® V ST D3 and D5 Devices. Note: CLK10 and CLK11 clock pins feed into FRACTIONALPLL_X183_Y63 and FRACTIONALPLL_X183_Y54.
  • PLL coordinates for Arria® V GT C3 and C7 devices are finalized. Removed the notes that state the PLL coordinates will be finalized in a future release of the Quartus® II software from the PLL locations diagrams.
January 2014 2014.01.10
  • Removed Preliminary tags for clock resources, clock input pin connections to GCLK and RCLK networks, and PLL features tables.
  • Updated clock resources table.
  • Added availability for RCLK[46..51] and RCLK[52..57] pins in RCLK networks diagram.
  • Added notes to dedicated clock input pin connectivity to GCLK and RCLK tables.
  • Added label for PLL strip in PLL locations diagrams.
  • Added descriptions for PLLs located in a strip.
  • Added PLL locations diagram for Arria® V SX B3 and B5 devices, and Arria® V ST D3 and D5 devices.
  • Added information on PLL migration guidelines.
  • Updated VCO post-scale counter, K, to VCO post divider.
  • Added information on PLL cascading.
  • Added information on programmable phase shift.
  • Updated automatic clock switchover mode requirement.
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Updated RCLK and PCLK clock sources per device quadrant.
  • Added link to Arria® V GZ Device Family Pin Connection Guidelines.
  • Updated RCLK and PCLK clock sources in hierarchical clock networks in each spine clock per quadrant diagram.
  • Added PCLK networks in clock network sources section.
  • Updated dedicated clock input pins in clock network sources section.
  • Updated information on clock power down.
  • Added information on C output counters for PLLs.
  • Added power down mode in PLL features table.
  • Added PLL physical counters information and diagram.
  • Marked PLL physical counters orientation in PLL locations diagrams.
  • Updated the fractional PLL architecture diagram to add dedicated refclk input port and connections.
  • Removed information on pfdena PLL control signal.
  • Updated the scaling factors for PLL output ports.
  • Updated the fractional value for PLL in fractional mode.
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Reorganized content.
November 2012 2012.11.19
  • Added note to indicate that the figures shown are the top view of the silicon die.
  • Updated clock resources for Arria® V GZ devices.
  • Added RCLK networks diagram for Arria® V GZ devices.
  • Restructured tables for clock input pin connectivity to the GCLK and RCLK networks.
  • Added table for clock input pin connectivity to the RCLK networks for Arria® V GZ devices.
  • Updated PCLK control block information.
  • Added PLL locations diagrams for Arria® V GZ E1, E3, E5, and E7 devices.
  • Removed information on PLL Compensation assignment in the Quartus II software.
  • Updated the fractional value for PLL in fractional mode.
  • Reorganized content and updated template.
June 2012 2.0
  • Restructured chapter.
  • Updated Figure 4–4, Figure 4–6, Figure 4–7, Figure 4–11, Figure 4–12, Figure 4–13, Figure 4–14, Figure 4–15, Figure 4–16, Figure 4–18, and Figure 4–19.
  • Updated Table 4–1, Table 4–2, Table 4–3, Table 4–4, and Table 4–5.
  • Added “Clock Regions”, “Clock Network Sources”, “Clock Output Connections”, “Clock Enable Signals”, “PLL Control Signals”, “Clock Multiplication and Division”, “Programmable Duty Cycle”, “Clock Switchover”, and “PLL Reconfiguration and Dynamic Phase Shift”.
November 2011 1.1 Restructured chapter.
May 2011 1.0 Initial release.