Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

8.2. MSEL Pin Settings

To select a configuration scheme, hardwire the MSEL pins to VCCPGM or GND without pull-up or pull-down resistors.

Note: Altera recommends connecting the MSEL pins directly to VCCPGM or GND. Driving the MSEL pins from a microprocessor or another controlling device may not guarantee the VIL or VIH of the MSEL pins. The VIL or VIH of the MSEL pins must be maintained throughout configuration stages.
Table 94.  MSEL Pin Settings for Each Configuration Scheme of Arria V Devices
Configuration Scheme Compression Feature Design Security Feature VCCPGM (V) 27 Power-On Reset (POR) Delay Valid MSEL[4..0] Device Variant Support
FPP x8 Disabled Disabled 1.8/2.5/3.0/3.3 Fast 10100 All
Standard 11000 All
Disabled Enabled 1.8/2.5/3.0/3.3 Fast 10101 All
Standard 11001 All
Enabled Enabled/Disabled 1.8/2.5/3.0/3.3 Fast 10110 All
Standard 11010 All
FPP x16 28 Disabled Disabled 1.8/2.5/3.0/3.3 Fast 00000 All
Standard 00100 All
Disabled Enabled 1.8/2.5/3.0/3.3 Fast 00001 All
Standard 00101 All
Enabled Enabled/Disabled 1.8/2.5/3.0/3.3 Fast 00010 All
Standard 00110 All
FPP x32 28 Disabled Disabled 1.8/2.5/3.0 Fast 01000 Arria® V GZ
Standard 01100 Arria® V GZ
Disabled Enabled 1.8/2.5/3.0 Fast 01001 Arria® V GZ
Standard 01101 Arria® V GZ
Enabled Enabled/Disabled 1.8/2.5/3.0 Fast 01010 Arria® V GZ
Standard 01110 Arria® V GZ
PS Enabled/Disabled Enabled/Disabled 1.8/2.5/3.0/3.3 Fast 10000 All
Standard 10001 All
AS (x1 and x4) Enabled/Disabled Enabled/Disabled 3.0/3.3 Fast 10010 All
Standard 10011 All
JTAG-based configuration Disabled Disabled Use any valid MSEL pin settings above All
Note: You must also select the configuration scheme in the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime software. Based on your selection, the option bit in the programming file is set accordingly.
27 The Arria® V GZ device does not support 3.3 V.
28 For configuration with HPS in SoC FPGA devices, refer to the FPGA Manager for the related MSEL pin settings.