Arria V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 7/24/2020
Public
Document Table of Contents

2.7. Byte Enable in Embedded Memory Blocks

The embedded memory blocks support byte enable controls:

  • The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
  • The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.
  • The byte enable registers do not have a clear port.
  • If you are using parity bits, on the M20K and M10K blocks, the byte enable function controls 8 data bits and 2 parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
  • The MSB and LSB of the byteena signal correspond to the MSB and LSB of the data bus, respectively.
  • The byte enables are active high.

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