Arria V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 7/24/2020
Document Table of Contents Non-DPA Mode

The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising edge of the serial LVDS_diffioclk clock that is produced by the left and right PLLs.

You can select the rising edge option with the Intel® Quartus® Prime IP Catalog. The LVDS_diffioclk clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.

The following figure shows the non-DPA datapath block diagram. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.

Figure 151. Receiver Data Path in Non-DPA Mode

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