18.104.22.168. Guideline: Using DPA-Enabled Differential Channels
Each differential receiver in an I/O block has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel. If you enable a DPA channel in a bank, you can use both single-ended I/Os and differential I/O standards in the bank.
You can place double data rate I/O (DDIO) output pins within I/O modules that have the same pad group number as a SERDES differential channel. However, you cannot place SDR I/O output pins within I/O modules that have the same pad group number as a receiver SERDES differential channel. You must implement the input register within the FPGA fabric logic.
The following figure illustrates the clock network for DPA and SERDES resources in Arria V devices.
If you use DPA-enabled channels in differential banks, adhere to the following guidelines.
Using Center and Corner PLLs
If two PLLs drive the DPA-enabled channels in a bank—the corner and center PLL drive one group each—there must be at least one row (one differential channel) of separation between the two groups of DPA-enabled channels, as shown in the following figure.
This separation prevents noise mixing because the two groups can operate at independent frequencies. No separation is necessary if a single PLL is driving both the DPA-enabled channels and DPA-disabled channels.
Using Both Center PLLs
You can use center PLLs to drive DPA-enabled channels simultaneously, if they drive these channels in their adjacent banks only, as shown in the previous figure. If one of the center PLLs drives the DPA-enabled channels in the left and right I/O banks in Arria V GX, GT, SX, or ST devices, you cannot use the other center PLL for DPA-enabled channels. If the center left PLL drives the DPA-enabled channels in the right I/O bank, the right center PLL cannot drive the DPA-enabled channels in the left I/O bank, and vice versa. The center PLLs cannot drive cross-banks simultaneously in Arria V GZ devices. Refer to the following figures.
Using Both Corner PLLs
You can use the left and right corner PLLs to drive DPA-enabled channels simultaneously, if they drive the channels in their adjacent banks only. There must be at least one row of separation between the two groups of DPA-enabled channels.
There are two PLL in each corner of the device. However, only one corner PLL can be use to drive DPA-enabled channels in a quadrant.
Because there is only a single DPA clock bus, a PLL drives a continuous series of DPA channels.
To prevent noise mixing, use one row of separation between two groups of DPA channels.
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