18.104.22.168. Input Registers
The input path consists of the DDR input registers and the read FIFO block. You can bypass each block of the input path.
There are three registers in the DDR input registers block. Registers A and B capture data on the positive and negative edges of the clock while register C aligns the captured data. Register C uses the same clock as Register A.
The read FIFO block resynchronizes the data to the system clock domain and lowers the data rate to half rate.
The following figure shows the registers available in the Arria® V input path. For DDR3 and DDR2 SDRAM interfaces, the DQS and DQSn signals must be inverted. If you use Altera’s memory interface IPs, the DQS and DQSn signals are automatically inverted.
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