Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Public
Document Table of Contents

3.5. Block Architecture

The Arria® V variable precision DSP block consists of the following elements:

  • Input register bank
  • Pre-adder
  • Internal coefficient
  • Multipliers
  • Adder
  • Accumulator and chainout adder
  • Systolic registers
  • Double accumulation register
  • Output register bank

If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.

Figure 24. Variable Precision DSP Block Architecture in 18 x 19 Mode for Arria V GX, GT, SX, and ST Devices


Figure 25. Variable Precision DSP Block Architecture in 27 x 27 Mode for Arria® V GX, GT, SX, and ST Devices


Figure 26. Variable Precision DSP Block Architecture in 18 x 18 Mode for Arria V GZ Devices


Figure 27. Variable Precision DSP Block Architecture in 27 x 27 Mode for Arria V GZ Devices