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1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices
2. Embedded Memory Blocks in Arria V Devices
3. Variable Precision DSP Blocks in Arria V Devices
4. Clock Networks and PLLs in Arria V Devices
5. I/O Features in Arria V Devices
6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices
7. External Memory Interfaces in Arria V Devices
8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices
9. SEU Mitigation for Arria V Devices
10. JTAG Boundary-Scan Testing in Arria V Devices
11. Power Management in Arria V Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Arria V Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Error Correction Code Support
2.11. Embedded Memory Blocks in Arria V Devices Revision History
3.6.1.1. 9 x 9 Independent Multiplier
3.6.1.2. 18 x 18 Independent Multiplier
3.6.1.3. 18 x 18 or 18 x 19 Independent Multiplier
3.6.1.4. 16 x 16 Independent Multiplier or 18 x 18 Independent Partial Multiplier
3.6.1.5. 18 x 25 Independent Multiplier
3.6.1.6. 20 x 24 Independent Multiplier
3.6.1.7. 27 x 27 Independent Multiplier
3.6.1.8. 36 x 18 Independent Multiplier
3.6.1.9. 36-Bit Independent Multiplier
4.2.1. PLL Physical Counters in Arria V Devices
4.2.2. PLL Locations in Arria® V Devices
4.2.3. PLL Migration Guidelines
4.2.4. Fractional PLL Architecture
4.2.5. PLL Cascading
4.2.6. PLL External Clock I/O Pins
4.2.7. PLL Control Signals
4.2.8. Clock Feedback Modes
4.2.9. Clock Multiplication and Division
4.2.10. Programmable Phase Shift
4.2.11. Programmable Duty Cycle
4.2.12. Clock Switchover
4.2.13. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O Resources Per Package for Arria® V Devices
5.2. I/O Vertical Migration for Arria® V Devices
5.3. I/O Standards Support in Arria V Devices
5.4. I/O Design Guidelines for Arria V Devices
5.5. I/O Banks Locations in Arria® V Devices
5.6. I/O Banks Groups in Arria V Devices
5.7. I/O Element Structure in Arria V Devices
5.8. Programmable IOE Features in Arria V Devices
5.9. On-Chip I/O Termination in Arria V Devices
5.10. External I/O Termination for Arria V Devices
5.11. I/O Features in Arria V Devices Revision History
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.4.2. Guideline: Use the Same VCCPD for All I/O Banks in a Group
5.4.3. Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank
5.4.4. Guideline: VREF Pin Restrictions
5.4.5. Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing
5.4.6. Guideline: Use PLL Integer Mode for LVDS Applications
5.4.7. Guideline: Pin Placement for General Purpose High-Speed Signals
5.8.1. Programmable Current Strength
5.8.2. Programmable Output Slew Rate Control
5.8.3. Programmable IOE Delay
5.8.4. Programmable Output Buffer Delay
5.8.5. Programmable Pre-Emphasis
5.8.6. Programmable Differential Output Voltage
5.8.7. Open-Drain Output
5.8.8. Pull-up Resistor
5.8.9. Bus-Hold Circuitry
6.1. Dedicated High-Speed Circuitries in Arria® V Devices
6.2. High-Speed I/O Design Guidelines for Arria® V Devices
6.3. Differential Transmitter in Arria V Devices
6.4. Differential Receiver in Arria V Devices
6.5. Source-Synchronous Timing Budget
6.6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices Revision History
7.4.1. UniPHY IP
7.4.2. External Memory Interface Datapath
7.4.3. DQS Phase-Shift Circuitry
7.4.4. Phase Offset Control for Arria® V GZ Devices
7.4.5. PHY Clock (PHYCLK) Networks
7.4.6. DQS Logic Block
7.4.7. Leveling Circuitry for Arria V GZ Devices
7.4.8. Dynamic OCT Control
7.4.9. IOE Registers
7.4.10. Delay Chains
7.4.11. I/O and DQS Configuration Blocks
7.5.1. Features of the Hard Memory Controller
7.5.2. Multi-Port Front End
7.5.3. Bonding Support
7.5.4. Hard Memory Controller Width for Arria V GX
7.5.5. Hard Memory Controller Width for Arria V GT
7.5.6. Hard Memory Controller Width for Arria V SX
7.5.7. Hard Memory Controller Width for Arria V ST
8.1. Enhanced Configuration and Configuration via Protocol
8.2. MSEL Pin Settings
8.3. Configuration Sequence
8.4. Configuration Timing Waveforms
8.5. Device Configuration Pins
8.6. Fast Passive Parallel Configuration
8.7. Active Serial Configuration
8.8. Using EPCS and EPCQ Devices
8.9. Passive Serial Configuration
8.10. JTAG Configuration
8.11. Configuration Data Compression
8.12. Remote System Upgrades
8.13. Design Security
8.14. Configuration, Design Security, and Remote System Upgrades in Arria V Devices Revision History
10.1. BST Operation Control
10.2. I/O Voltage for JTAG Operation
10.3. Performing BST
10.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
10.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
10.6. IEEE Std. 1149.1 Boundary-Scan Register
10.7. IEEE Std. 1149.6 Boundary-Scan Register
10.8. JTAG Boundary-Scan Testing inArria V Devices Revision History
11.1. Power Consumption
11.2. Programmable Power Technology
11.3. Temperature Sensing Diode
11.4. Hot-Socketing Feature
11.5. Hot-Socketing Implementation
11.6. Arria V GX, GT, SX, and ST Power-Up Sequence
11.7. Arria V GZ Power-Up Sequence
11.8. Power-On Reset Circuitry
11.9. Power Management in Arria V Devices Revision History
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10.1.2. Supported JTAG Instruction
JTAG Instruction | Instruction Code | Description |
---|---|---|
SAMPLE / PRELOAD | 00 0000 0101 |
|
EXTEST | 00 0000 1111 |
|
BYPASS | 11 1111 1111 | Places the 1-bit bypass register between the TDI and TDO pins. During normal device operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices. |
USERCODE | 00 0000 0111 |
|
IDCODE | 00 0000 0110 |
|
HIGHZ | 00 0000 1011 |
|
CLAMP | 00 0000 1010 |
|
PULSE_NCONFIG | 00 0000 0001 | Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is not affected. |
CONFIG_IO | 00 0000 1101 | Allows I/O reconfiguration (after or during reconfigurations) through the JTAG ports using I/O configuration shift register (IOCSR) for JTAG testing. You can issue the CONFIG_IO instruction only after the nSTATUS pin goes high. |
LOCK | 01 1111 0000 | Put the device in JTAG secure mode. In this mode, only BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, SHIFT_EDERROR_REG , and UNLOCK instructions are supported. This instruction can only be accessed through JTAG core access in user mode. It cannot be accessed through external JTAG pins in test or user mode. |
UNLOCK | 11 0011 0001 | Release the device from the JTAG secure mode to enable access to all other JTAG instructions. This instruction can only be accessed through JTAG core access in user mode. It cannot be accessed through external JTAG pins in test or user mode. |
KEY_CLR_VREG | 00 0010 1001 | Clears the volatile key. |
KEY_VERIFY | 00 0001 0011 | Verifies the non-volatile key has been cleared. |
EXTEST_PULSE 36 | 00 1000 1111 | Enables board-level connectivity checking between the transmitters and receivers that are AC coupled by generating three output transitions:
The EXTEST_PULSE JTAG instruction is only supported in user mode for Arria V GZ devices. |
EXTEST_TRAIN 36 | 00 0100 1111 | Behaves the same as the EXTEST_PULSE instruction except that the output continues to toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/IDLE state. The EXTEST_TRAIN JTAG instruction is only supported in user mode for Arria V GZ devices. |
Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high.
Note: If you use DC coupling on HSSI signals, execute the EXTEST instruction. If you use AC coupling on HSSI signals, execute the EXTEST_PULSE instruction. AC-coupled and DC-coupled HSSI are only supported in post-configuration mode.
Related Information
36 This instruction is only supported by Arria V GZ devices.
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