Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Public
Document Table of Contents

9.5.3. Error Detection Registers

This section describes the registers used in user mode.

Figure 216. Block Diagram for Error Detection in User ModeThe block diagram shows the registers and data flow in user mode.


Table 111.  Error Detection Registers
Name Width (Bits) Description
Syndrome register 32 Contains the 32-bit CRC signature calculated for the current frame. If the CRC value is 0, the CRC_ERROR pin is driven low to indicate no error. Otherwise, the pin is pulled high.
Error message register (EMR) 67 Contains error details for single-bit and double-adjacent errors. The error detection circuitry updates this register each time the circuitry detects an error. The Error Message Register Map figure shows the fields in this register and the Error Type in EMR table lists the possible error types.
JTAG update register 67 This register is automatically updated with the contents of the EMR one clock cycle after the content of this register is validated. The JTAG update register includes a clock enable, which must be asserted before its contents are written to the JTAG shift register. This requirement ensures that the JTAG update register is not overwritten when its contents are being read by the JTAG shift register.
JTAG shift register 67 This register allows you to access the contents of the JTAG update register via the JTAG interface using the SHIFT_EDERROR_REG JTAG instruction.
User update register 67 This register is automatically updated with the contents of the EMR one clock cycle after the contents of this register are validated. The user update register includes a clock enable, which must be asserted before its contents are written to the user shift register. This requirement ensures that the user update register is not overwritten when its contents are being read by the user shift register.
User shift register 67 This register allows user logic to access the contents of the user update register via the core interface.
JTAG fault injection register 46 You can use this register with the EDERROR_INJECT JTAG instruction to inject errors in the bitstream. The JTAG Fault Injection Register Map table lists the fields in this register.
Fault injection register 46 This register is updated with the contents of the JTAG fault injection register.
Figure 217. Error Message Register Map


Table 112.  Error Type in EMRThe following table lists the possible error types reported in the error type field in the EMR.
Error Type Description
Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 No CRC error.
0 0 0 1 Location of a single-bit error is identified.
0 0 1 0 Location of a double-adjacent error is identified.
1 1 1 1 Error types other than single-bit and double-adjacent errors.
Table 113.  JTAG Fault Injection Register Map
Field Name Bit Range Description
Error Byte Value 31:0 Contains the location of the bit error that corresponds to the error injection type to this field.
Byte Location 41:32 Contains the location of the injected error in the first data frame.
Error Type 45:42 Specifies the following error types.
Bit 45 Bit 44 Bit 43 Bit 42
0 0 0 0 No error
0 0 0 1 Single-bit error
0 0 1 0 Double adjacent error