Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Document Table of Contents

4.2.6. PLL External Clock I/O Pins

Two adjacent fractional PLLs share four dual-purpose clock I/O pins, organized as one of the following combinations:

  • Four single-ended clock outputs
  • Two single-ended outputs and one differential clock output
  • Four single-ended clock outputs and two single-ended feedback inputs in the I/O driver feedback for zero delay buffer (ZDB) mode support
  • Two single-ended clock outputs and two single-ended feedback inputs for single-ended external feedback (EFB) mode support
  • One differential clock output and one differential feedback input for differential EFB support (only one of the two adjacent fractional PLLs can support differential EFB at one time while the other fractional PLL can be used for general-purpose clocking)
Note: The middle fractional PLLs on the left and right sides of Arria® V GX B5 and B7 devices, and Arria® V GT D7 device do not support external clock outputs.

The following figure shows that any of the output counters (C[0..17] ) or the M counter on the PLLs can feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins available from a given PLL.

Figure 84. Dual-Purpose Clock I/O Pins Associated with PLL for Arria V Devices

Each pin of a single-ended output pair can be either in-phase or 180° out-of-phase. To implement the 180° out-of-phase pin in a pin pair, the Intel® Quartus® Prime software places a NOT gate in the design into the IOE.

The clock output pin pairs support the following I/O standards:

  • Same I/O standard for the pin pairs
  • LVDS
  • Differential high-speed transceiver logic (HSTL)
  • Differential SSTL

Arria® V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not require external PLL clocking.