Issue 338064: Volume 1, Chapter 9 SEU Mitigation for Arria® V Devices, Version 2015.06.12
In page 9-8, Timing section states as follows:
The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles.
But this is incorrect. It should state as follows:
The CRC_ERROR pin is always driven low during CRC calculation. When an error occurs, the EDCRC hard block takes 32 clock cycles to update the EMR, the pin is driven high once the EMR is updated. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for 32 clock cycles.
Figure 9-5 states CRC Calculation (minimum 32 clock cycles), but it should state CRC Calculation (32 clock cycles).
Issue 162661: Configuration, Design Security, and Remote System Upgrades in Arria V Devices, Version 2013.6.11
Page 8-6 states "The supported configuration voltages are 2.5, 3.0, and 3.3 V for all Arria V devices except for Arria V GZ devices. The supported configuration voltages for Arria V GZ devices are 2.5 and 3.3 V."
This is incorrect, Arria V GZ devices support 2.5 and 3.0 V.
Issue 156379: Clock Networks and PLLs in Arria V Devices, Version 2013.05.06
There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says:
"Both clock inputs must be running."
The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say:
"Both clock inputs must be running when the FPGA is configured."
Issue 137947: I/O Features in Arria V Devices, Version 2013.6.21
Table 5-11 indicates the 3.3V input signal is not supported when VCCIO=2.5V in MuliVolt I/O Support. The table is incorrect and the 2.5V VCCIO can support a 3.3V input signal.
Issue 140058: Arria V Device Datasheet, version 3.3
fout for an -3 speed grade device is missing in table 25. fout for a -3 speed grade device is the same as a -4 speed grade device.
Issue 87336: I/O Features in Arria V Devices, version 2012.12.04
In Table 5.24, the selectable I/O Standard for Rt OCT with Calibration shows the Rt OCT of SSTL-15 Class I, Class II and SSTL-15 (Ohms) is 20/25/30/40/50/60/120 is incorrect. The table will be updated to reflect as below:
The Rt OCT with calibration on following I/O standard should be corrected:
SSTL-15 Class I – 50 Ohms
SSTL-15 Class II – 50 Ohms
SSTL-15 – 20, 30, 40, 60, 120 Ohms
Issue 41645: Device Interfaces and Integration Basics for Arria V Devices, version 1.2
This chapter has been integrated to the device handbook, updates include the removal of 1.8V as a valid power supply for Active serial configuration.
Issue 44730: I/O Features in Arria V Devices, version 1.2
OCT for 1.5V LVCMOS outputs is supported.
Issue 32735: I/O Features in Arria V Devices, version 1.0
Note 2 for table 5-4 updated to recommend using the on-chip clamp diode when the input signal is 3.0V or 3.3V.
Issue 391244: I/O Features in Arria V Devices, version 1.0
Table 5-3 updated to show the only supported current strength for 3.3V LVCMOS is 2mA.
Issue 391245: I/O Features in Arria V Devices, version 1.0
Table 5-3 updated to show the supported current strengths for 3.3V LVTTL is 4mA and 8mA.