1.1. Key Advantages of Arria® V Devices
1.2. Summary of Arria® V Features
1.3. Arria® V Device Variants and Packages
1.4. I/O Vertical Migration for Arria® V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.12. Low-Power Serial Transceivers
1.13. SoC with HPS
1.14. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History
1. Arria V Device Overview
The Arria® V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-range FPGA bandwidth 12.5 Gbps transceivers.
The Arria® V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (DSP) applications.
Section Content
Key Advantages of Arria V Devices
Summary of Arria V Features
Arria V Device Variants and Packages
I/O Vertical Migration for Arria V Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
PCIe Gen1, Gen2, and Gen 3 Hard IP
External Memory Interface
Low-Power Serial Transceivers
SoC with HPS
Dynamic Reconfiguration
Enhanced Configuration and Configuration via Protocol
Power Management
Document Revision History
Related Information