Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.3.5.2. Maximum Resources

Table 12.  Maximum Resource Counts for Arria V ST Devices
Resource Member Code
D3 D5
Logic Elements (LE) (K) 350 462
ALM 132,075 174,340
Register 528,300 697,360
Memory (Kb) M10K 17,290 22,820
MLAB 2,014 2,658
Variable-precision DSP Block 809 1,090
18 x 18 Multiplier 1,618 2,180
FPGA PLL 14 14
HPS PLL 3 3
Transceiver 6-Gbps 30 30
10-Gbps 9 16 16
FPGA GPIO10 540 540
HPS I/O 208 208
LVDS Transmitter 120 120
Receiver 136 136
PCIe Hard IP Block 2 2
FPGA Hard Memory Controller 3 3
HPS Hard Memory Controller 1 1
ARM Cortex-A9 MPCore Processor Dual-core Dual-core
9 Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture in Arria V Devices chapter.
10 The number of GPIOs does not include transceiver I/Os. In the Intel® Quartus® Prime software, the number of user I/Os includes transceiver I/Os.

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