Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.9. FPGA General Purpose I/O

Arria® V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:

  • Programmable bus hold and weak pull-up
  • LVDS output buffer with programmable differential output voltage (VOD ) and programmable pre-emphasis
  • On-chip parallel termination (RT OCT) for all I/O banks with OCT calibration to limit the termination impedance variation
  • On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity
  • Unused voltage reference ( VREF ) pins that can be configured as user I/Os ( Arria® V GX, GT, SX, and ST only)
  • Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture

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